The present invention relates to a method and/or architecture for implementing level shifters generally and, more particularly, to a method and/or architecture for implementing inverting level shifters with start-up circuits.
With ever increasing digital clock speeds, faster digital translation circuits are required for multi-voltage designs. Conventional digital translation circuits that level shift digital signals up to higher voltages are generally too slow for high speed operation (i.e., 650 MHz or higher). Slower conventional level shifting circuits (such as 4 transistors with cross coupled PMOS devices) are used in digital, analog, and mixed signal multi-voltage designs. Such conventional level shifting circuits often fail since they do not provide full output swing at high speeds and extreme process corners.
It would be desirable to provide a high speed (e.g., 650 MHz or higher) level shifting function for digital signals to translate lower voltage signals (e.g., 0 to 1.5 v) to higher voltages (e.g., 0 to 3.3 v) while adding a minimal amount of jitter (e.g., less than 2 ps).
The present invention concerns an apparatus comprising a control circuit and a logic circuit. The control circuit may be configured to receive an input signal and an indication signal and present a complement of the input signal. The logic circuit may be configured to receive the complementary input signal and generate an output signal. The output signal may provide a larger full scale output swing than the input signal since the output signal may be on a voltage supply with a higher voltage.
The objects, features and advantages of the present invention include the implementation of an inverting level shifter with a start-up circuit that may (i) be capable of high speed level shifting (e.g., clock speeds greater than 650 Mhz) from lower supply voltages to higher supply voltages, (ii) provide full scale output voltages (e.g., swings from VSS to VDD2), (iii) allow output clocks to charge down to zero volts, (iv) provide output voltage levels from VSS to VDD2, (v) provide low power consumption, (vi) eliminate static power dissipation, (vii) operate from two power supplies (e.g., 1.5V and 3.3V), (viii) implement a startup circuit that may provide correct start up operation, (ix) implement a capacitor as a bootstrap device, and/or (x) allow a capacitor to be charged on a transition of an input.